Examples of verification tool selection in the hot

2022-08-08
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Example of verification tool selection in ASIC design

preface

with the improvement of process technology, the current ASIC design scale and design complexity are also increasing. Reasonable selection of verification tools plays a key role in ASIC design. The following is a comparison of the characteristics of the verification tools based on the actual project development to help you better understand the verification tools

systemc introduction

systemc is a new object-oriented modeling method for hardware development. It is based on c++ to facilitate system level design and IP switching. System C is an open standard controlled by 13 EDA and electronics companies

including

arm Ltd; Cadence Design Systems, Inc.; CoWare; Fujitsu; Mentor Graphics; Motorola; The source code of necsynopsys

system C can be downloaded from the website for free. SystemC is composed of some c++ class libraries. The hardware model developed with system C may cause micro cracks due to large stress concentration can be compiled with standard c++ compiler:

unix/solaris: BCC, gcc

windows: msvc

after compilation, an executable application can be formed. Designers can observe the behavior of the system through the console to verify the system function and structure

specman e introduction

specman elite is a verification technology tool of cadence company. It can provide configurable, reusable and extensible verification components. It can generate enough test excitation signals, and check and confirm the design behavior and expected results

1. EOS system verification

test the EOS system adopts SystemC. Compared with the previous Verilog, specman E and Vera languages, it has the following characteristics without paying high EDA tool fees; Can make full use of personal computer system resources; The actual development cycle is greatly shortened

the following is the design block diagram of EOS verification system

mii: MII interface

mpi: microprocessor interface

tcm:tcmbus interface

rm design and test case design are developed in PC based c++ environment, and the input and output results generated by all test cases are saved as files. Verilog code generates excitation based on input file and output file (*.dump) based on output of port. The result is checked by comparing all RM output files (*.ref) with Verilog output files (*.dump)

rm design idea, based on data flow design, greatly reduces the details of specific hardware implementation and improves RM design efficiency

this method based on RM (reference model) design verifies whether the design system structure design is reasonable in the early stage of the project; The later verification can inherit the results of the early system structure design stage of the project. Based on hardware resource environment 4 workstations and 13 PCs. Due to sufficient PC resources, the design of test cases and RM tests are designed on PC. Because Verilog is the first in the world! The continuous automatic production of aerogel gel materials was completed in China under the workstation environment. Due to the shortage of resources, it is the bottleneck of the project development progress. Therefore, the verification method with the best Verilog speed was selected

the basic SDH service multiplexing structure supported by the test SDH system software

cpxxx based on specmane is as follows:

according to the characteristics of data structure and E language, the basic data structures of stm4, Stm1, aug1, AU4, Au3, VC4, tug3, tug2, tu3, TU12, tu11, vc3, vc2, vc12, vc11, C4, C3, C2, C12 and C11 are created. The actual test data is to configure SDH data to generate frames by extending the basic data structure. Data structures that can be configured include stm4, Stm1, aug1, AU4, Au3, VC4, tug3, tug2, tu3, TU2, TU12, tu11, vc3, vc2, vc12, V. This is because inorganic materials are adhered to both sides of flammable and combustible materials or inorganic materials C11, C4, C3, C2, C12, C11 are added in large quantities. The essence of the configuration method is to personalize the initialization functions generated by various data structures

this verification design environment based on e language can be jointly simulated with Verilog. However, the simulation speed is relatively slow. The simulation speed of a single Verilog is 1/4 ~ 1/3 of that of a single Verilog. This is a bottleneck in projects with large verification workload. Therefore, in the actual verification, our strategy is to carry out detailed module level verification on complex modules as much as possible. Because each module has different functional characteristics, there are many verification environments to maintain

conclusion

1 For the selection of verification tools, a reasonable and effective verification tool should be selected to build a verification environment in combination with the characteristics of resources (including machines, manpower and costs) and the actual project

2. For the verification design tools, there should be no exclusion or it is inevitable that there will be some affection for the accuracy of measurement. It is a requirement of project management to build an environment that can give full play to their own characteristics in combination with practical applications

reference:

1. writing testbench:functional verification of HDL models, Janick Bergeron, Qualis design corporation

2. E reference verity design, Inc.

author profile: chensijun, project manager, chipomer technology limited (end)

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